1. Field of the Invention
The present invention relates to a method for programming the memory cells of a multi-level non-volatile memory device.
More particularly, the invention relates to a method of programming a non-volatile memory device of the multi-level type, which device comprises a plurality of transistor cells grouped into memory words and provided with conventional gate and drain terminals.
The invention relates, particularly but not exclusively, to a multi-level non-volatile memory device monolithically integrated in a semiconductor, and the following description is made with reference to this application field for convenience of illustration only.
2. Description of the Related Art
As it is well known, in a two-level memory device that employs a floating gate MOS transistor as elementary cell, the threshold voltage of the cell can be modulated to establish either of two logic states. A first logic state (logic “1”) corresponds to a situation of the floating gate containing no charge, as is typical of a virgin or an erased cell, for example. Another logic state (logic “0”) corresponds to the floating gate storing a sufficient number of electrons to produce a dramatic rise of its threshold, thereby denoting the programmed state of the cell.
A current-read method can be used for reading a memory cell 1, which consists of applying a read voltage Vread to the gate terminal of the cell and reading the current that flows through the cell:                if the cell is a written cell, its threshold voltage will be higher than the read voltage Vread, so that no current will flow through the cell; otherwise        if the cell is an erased cell, its threshold voltage must be adequate to admit a current through the cell.        
To read information contained in memory cells of this type, a sense amplifier is used which compares the cell current with a reference value, thus converting the analog information of the addressed data in the cell, i.e. the value of the cell threshold voltage, to digital information, i.e. to a logic “0” or a logic “1”.
Non-volatile memory devices, particularly those of the EEPROM and FLASH types, are specially adapted to store large amounts of data, and are widely used, for example, in the presently expanding digital video and audio fields. In fact, digital video and audio applications require higher and higher storage capacities in order to store a large number of musical songs in the same support, or to enhance image quality, such as by an increased number of imaging pixels.
Multi-level non-volatile memories have recently appeared on the market, which are memories capable of storing a multiplicity of information bits in each cell. Such memories look specially well equipped to fill the above demands.
In this type of multi-level memories, the charge stored in the floating gate is further broken up, thereby generating a number 2nb of distributions, where “nb” is the number of bits that are to be stored in a single cell. For example, with 2 bits per cell, the read sense amplifier is to process four distributions, instead of two as in the two-level instance.
A comparison of the threshold voltage distribution for a two-level (0,1) memory and a multi-level (00,01,10,11) memory with two bits per cell is schematically illustrated in FIGS. 4A and 4B. It can be seen that the multi-level structure decreases the gap between the voltage values and increases the read voltage.
It should be noted that the working range of the threshold voltage is independent of the number of bits contained in the cell. Thus, by employing a multi-level structure, the threshold gap between the various distributions decreases.
Reducing the gap between the threshold voltage distributions means reducing the current differences that the sense amplifier is to sense. Furthermore, it should be provided a programming method, able to place the cells inside the various distributions.
For convenience of illustration only, the instance of a flash EEPROM with NOR architecture will be considered herein below.
As it is well known, memory cells of this type are written by hot electron injection, by applying a voltage of about 10 V to the control gate terminal, a voltage of about 5 V to the drain terminal, and by leaving the source terminal connected to a ground reference, thereby allowing the floating gate terminal to accumulate charge to saturation.
In the instance of a multi-level memory, the reduction of the difference between the threshold voltages corresponding to the various charge levels that can be stored in the floating gate terminal, and hence the difference between the various conduction levels of the cells, requires an accurate and “fine” control of the cell programming operation, and in particular of the charge stored in the floating gate terminal during such an operation.
It has been shown, both theoretically and experimentally, that a linear relation exists between the variation ΔVG of the voltage applied to the control gate terminal during the cell programming phase and the threshold jump that is obtained at set values of the voltage VD applied to the drain terminal and of the voltage VS to the source terminal, as explained by Riccò et al. in an article “Nonvolatile Multilevel Memories For Digital Application”, Pro. IEEE, vol. 86, December, 1998, pages 2399-2421, which is incorporated herein by reference in its entirety.
In particular, as schematically shown in FIG. 1, the cell should be programmed by applying, to its control gate terminal, a “stepwise” voltage that increases linearly and applying a constant voltage (Vd1=Vd2=Vd3=Vd4=Vd5=Vd6=Vd7) to the drain terminals.
In practice, a series of program pulses are used which differ from each other by a constant value ΔVG. Thus, the program voltage is a constant pitch stepwise ramp, while the voltage on the drain terminal and the pulse duration are dependent on and set by the cell fabrication process.
At the end of each program pulse, the result is verified to see if the desired threshold level has been attained, and to discontinue or to continue programming accordingly.
It can be appreciated that, when this programming method is used, a threshold voltage distribution of width ΔVG is obtained, which equals the pitch of the stepwise program voltage.
Thus, multi-level memory cells can be programmed at a desired threshold voltage by using a predetermined number of program pulses.
The main problem encountered with the above method is its inherently low speed. Programming multi-level cells involves applying a succession of pulses to the control gate of the cell, starting from the lowest level, and this takes a longer time than the single programming pulse used in the case of two-level cells. In addition, each level is attained only after the setting of the level directly below.
In order to achieve a programming time of the single byte that can be compared with that of a conventional two-level cell, it has been thought of programming several multi-level cells in parallel.
Assuming 8 μs to be the time taken to program a single byte in the two-level case, and 200 μs to be the time taken to go through the stepwise program ramp in the multi-level case, then 256 bits of multi-level cells would have to be programmed simultaneously in order to achieve an effective programming time of 6 μs per each single byte of multi-level cells.
Increasing the internal parallelism of multi-level memory devices would bring about several technical problems, first and foremost increased current usage, to the point that any engineering developments in that direction would be restrained.
As an alternative to the previous solution it has been proposed to write a multi-level non-volatile memory device comprising a plurality of transistor cells grouped into memory words and provided with conventional gate and drain terminals by different drain voltage values applied in parallel to separate cells for attaining different threshold values.
This solution is disclosed for instance in the U.S. Pat. No. 5,796,652 assigned to NEC which discloses a memory cell array including first and second writing circuits generating first and second writing voltages having a level corresponding to the value of first and second quaternary input data.
So, two items of quaternary data can be simultaneously written into two multi-level memory cells of one memory row selected by one word line.
The principle of operation for writing multivalue information into the memory cells is disclosed with reference to FIG. 9 of the NEC patent. The gate of each selected memory cell transistor receives a negative writing voltage while the drain of the same transistor receives one of the available four voltages corresponding to the desired threshold voltages.
However, as shown in FIG. 10 of that patent, the writing bit line voltages are applied for a programming time Tp that is difficult to control and will not be able to reach always the target values without overlapping with or getting closer to different logic values of the cell.
Moreover, the circuit structure for applying the require writing voltages is very complex and uses a couple of switch transistors for each bit line to bias.
Similar solutions are disclosed also in the U.S. Pat. No. 5,708,600 and in the U.S. Pat. No.5.970,012, both of which are incorporated herein in their entireties. Both solution, however, fail to reach efficient programming results in reasonable times of with writing circuit of reduced complexity.